AD9553SLASHPCBZ datasheet(6/44 Pages) AD

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AD9553

Rev. 0 | Page 6 of 44

OUTPUT CHARACTERISTICS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL MODE

Differential Output Voltage

Swing

690

800

890

Output driver static (for dynamic performance, see

Figure 13).

Common-Mode Output

Voltage

VDD − 1.66

VDD − 1.34

VDD − 1.01

Output driver static.

Frequency Range

810

MHz

Duty Cycle

Up to 805 MHz output frequency.

Rise/Fall Time1 (20% to 80%)

255

305

100 Ω termination between the output driver pins.

LVDS MODE

Differential Output Voltage

Swing

Output driver static (for dynamic performance, see

Figure 13).

Balanced, VOD

297

398

Voltage swing between output pins; output driver static.

Unbalanced, ΔVOD

8.3

Absolute difference between voltage swing of normal pin and

inverted pin; output driver static.

Offset Voltage

Common Mode, VOS

1.17

1.35

Output driver static.

Common-Mode Difference,

ΔVOS

7.3

Voltage difference between output pins; output driver static.

Short-Circuit Output Current

Frequency Range

810

MHz

Duty Cycle

Up to 805 MHz output frequency.

Rise/Fall Time1 (20% to 80%)

285

355

100 Ω termination between the output driver pins.

CMOS MODE

Output Voltage High, VOH

Output driver static; standard drive strength setting.

IOH = 10 mA

2.8

IOH = 1 mA

2.8

Output Voltage Low, VOL

Output driver static; standard drive strength setting.

IOL = 10 mA

0.5

IOL = 1 mA

0.3

Frequency Range

200

MHz

3.3 V CMOS; standard drive strength setting. Output toggle

rates in excess of the maximum are possible, but with reduced

amplitude (see

Figure 12).

Duty Cycle

At maximum output frequency.

Rise/Fall Time1 (20% to 80%)

500

745

3.3 V CMOS; standard drive strength setting; 10 pF load.

1 The listed values are for the slower edge (rise or fall).

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