X88C75PI datasheet(4/27 Pages) XICOR

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X88C75 SLIC® E2

Page Write Operation

Toggle Bit Polling

Because the X88C75 typical write timing is less than the

specified 5ms, Toggle Bit Polling has been provided to

determine the early completion of a write cycle. During

the internal programming cycle, I/O6 will toggle from “1”

to “0” and “0” to “1” on subsequent attempts to read from

the memory plane that is being updated. When the

Figure 1. Toggle Bit Polling

internal cycle is complete, the toggling will cease and

the device will be accessible for additional read or write

operations. Due to the dual plane architecture, reads for

polling must occur from the plane that was written; that

is, the state of A12 during a write must match the state

of A12 during polling.

tBLC

ALE

A/D0–A/D7

A8–A12

PSEN(RD)

AIN

DIN

A12=n

OPERATION

BYTE 0

BYTE 1

BYTE 2

LAST BYTE

READ (1)(2)

AFTER tWC READY FOR

NEXT WRITE OPERATION

tWC

2887 ILL F04

AIN

DIN

A12=n

AIN

DIN

A12=n

AIN

DIN

A12=n

AIN DOUT

A12=x

AIN

ADDR

AIN

Next Address

LAST BYTE

WRITTEN

ALE

A/D0–A/D7

A8–A12

AIN

DIN

A12=n

OPERATION

AIN DOUT

A12=n

AIN DOUT

A12=n

AIN DOUT

A12=n

AIN DOUT

A12=x

AIN

ADDR

I/O6=X

X88C75 READY FOR

NEXT OPERATION

2887 ILL F05

I/O6=X

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