Production Data

WM9701A

WOLFSON MICROELECTRONICS LTD.

PD Rev 3.2 January 2001

15

stream in the audio output frame. At this point in time it is assumed that all sources of audio input

have also been neutralised.

The AC’97 controller should also drive SYNC and SDATA_OUT low after programming WM9701A to

this low power, “halted” mode.

Once WM9701A has been instructed to halt BIT_CLK, a special “wake up” protocol must be used to

bring the AC-link to the active mode since normal audio output and input frames can not be

communicated in the absence of BIT_CLK.

WAKING UP THE AC-LINK

There are 2 methods for bringing the AC-link out of a low power, halted mode. Regardless of the

method, it is the AC’97 controller that performs the wake up task.

AC-link protocol provides for a “Cold WM9701A Reset”, and a “Warm WM9701A Reset”.

The current power down state would ultimately dictate which form of WM9701A reset is appropriate.

Unless a “cold” or “register” reset (a write to the Reset register) is performed, wherein the WM9701A

registers are initialised to their default values, registers are required to keep state during all power

down modes.

Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur

for a minimum of 4 audio frame times following the frame in which the power down was triggered.

When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).

COLD WM9701A RESET

A cold reset is achieved by asserting RESETB for the minimum specified time. By driving RESETB

low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and all

WM9701A control registers will be initialised to their default power on reset values.

RESETB is an asynchronous WM9701A input.

WARM WM9701A RESET

A warm WM9701A reset will re-activate the AC-link without altering the current WM9701A register

values. A warm reset is signaled by driving SYNC high for a minimum of 1

µS in the absence of

BIT_CLK.

Within normal audio frames SYNC is a synchronous WM9701A input. However, in the absence of

BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to

WM9701A. WM9701A will not respond with the activation of BIT_CLK until SYNC has been sampled

low again by WM9701A. This will preclude the false detection of a new audio frame.

SERIAL INTERFACE REGISTER MAP DESCRIPTION

(See Table 10)

The serial interface bits perform control functions described as follows: The register map is fully

specified by the AC’97 specification, and this description is simply repeated below, with optional

unsupported features omitted.

RESET REGISTER (INDEX 00h)

Writing any value to this register performs a register reset, which causes all registers to revert to

their default values. Reading this register returns the ID code of the part, indication of modem

support (not supported by WM9701A) and a code for the type of 3D Stereo Enhancement (not

supported by WM9701A).