Production Data

WM2632

WOLFSON MICROELECTRONICS LTD

PD Rev 1.1 April 2001

5

Test Characteristics:

recommended operating free-air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Reference Configured as Input

Reference input resistance

50

k

Ω

Reference input capacitance

10

pF

Reference feedthrough

+ 2.048V DC, DAC code 0

-84

dB

Reference input bandwidth

DAC code 128

Slow

Fast

1.9

2.2

MHz

MHz

Reference Configured as Output

Low reference voltage

1.010

1.024

1.040

V

High reference voltage

VDD > 4.75V

2.020

2.048

2.096

V

Output source current

1mA

Output sink current

-1

mA

Load Capacitance

in parallel with 100nF cap.

1

10

µF

PSRR

60

dB

Digital Inputs

High level input current

Input voltage = DVDD

-1

1

µA

Low level input current

Input voltage = 0V

-1

1

µA

Input capacitance

8pF

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding

the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change

of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same

direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the

proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10k

Ω load and 2kΩ

load. It is expressed as a percentage of the full scale output voltage with a 10k

Ω load.

supply current will increase.

9. Slew rate results are for the lower value of the rising and falling edge slew rates.

10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and

falling edges. Limits are ensured by design and characterisation, but are not production tested.