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WM2331CDT/V bảng dữ liệu(PDF) 7 Page - Wolfson Microelectronics plc |
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WM2331CDT/V bảng dữ liệu(HTML) 7 Page - Wolfson Microelectronics plc |
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7 / 25 page ![]() Production Data WM2331 WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 7 WR Output hi - Z Input hi - Z Output OEB tDZ t OEW tWRP tWOE tDH tDS tDEN DIO[9:0] Note: All timing measurements are based on 50% of edge transition Figure 1 Write Timing Sample 1 Sample 5 Sample 4 Sample 3 Sample 2 tCLK tCL tCH Digital Output tD Pipeline Delay Sample 1 Sample 2 Note: All timing measurements are based on 50% of edge transition CLK Analogue Input at AIN Figure 2 Output Timing Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Clock Clock period tCLK 33 ns Clock high time tCH 15 16.5 ns Clock low time tCL 15 16.5 ns Timing Pipeline delay 3 CLK cycles Clock to data valid tD 25 ns Output disable to hi-Z output tDZ 020 ns Output enable to data valid tDEN 020 ns Output disable to write enable tOEW 12 ns Write disable to output enable tWOE 12 ns Write pulse width tWRP 15 ns Input data setup time tDS 5ns Input data hold time tDH 5ns |
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