The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high.

DRF1201

The Test Circuit illustrated above was used to evaluate the DRF1201 (available as an evaluation Board DRF12XX / EVALSW.) The input con-

trol signal is applied to the DRF1201 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal

ground currents.

The +V

for this function must be capable of supporting the RMS currents and frequency of the gate load. R

evaluate the output performance of the DRF1201.

Figure 2, DRF1201 Test Circuit

FN (pin 3)*

IN (pin 4)*

MOSFET

HIGH

HIGH

ON

HIGH

LOW

OFF

LOW

HIGH

OFF

LOW

LOW

ON

Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583

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