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●Description of operations

BH7659FS

1) Analog SW block

R, G, and B chroma signals are switched in two channels.

INA is selected by applying a high-level voltage to the CTL pin, and INB is selected by applying a low-level voltage.

When the power save pin (pin 8) is set to high level, the current to the SW block's output transistors is reduced to lower

the circuit current.

Even during low power mode, signal switching can be performed normally as long as there is no drop in frequency

characteristics.

2) CMOS analog SW block

SDA and SDC signals are switched via an I

exchange information bidirectionally between a computer and a monitor.

The switching circuits used by this IC handle are configured as CMOS analog switches in order to handle I

signals and to transmit input and output signals bidirectionally. (ON resistance: Ron 200 Ω typ.)

●Application circuit

BH7659FS

SCL IO

+

C2

C1

Ro

Ro

Ro

R3

R3

R3

R3

R3

R3

R3

R3

R3

SDA IO

R OUT

G OUT

B OUT

HD OUT

+

C2

C1

+

C2

C1

R

G

A

A

B

B

A

B

B

A

B

A

AA

B

B

B

C2

R1

R4

5. 1

Input A

R

G

B

VD

SDA

SCA

HD

Input B

R

G

B

VD

SDA

SCA

HD

R2

C1

C2

R1

R2

C1

C2

R1

R2

C1

C2

C3

R1

R2

R4

PS:H

C1

C2

C2

R1

R2

C1

C2

R1

R2

R4

R3

R3

R3

VD OUT

C3

CTL

IN A: H

IN B: L

N. C.

N. C.

C1

C1

R4

5. 1

R4

5. 1

R4

5. 1

R4

5. 1

R4

5. 1

R4

5. 1

R4

5. 1

POWER

SAVE

CTL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

+

Fig.9