LTC2942CDCB datasheet(13/16 Pages) LINER

13 / 16 page

LTC2942

2942f

APPLICATIONS INFORMATION

Data Transmission

After a START condition, the I2C bus is considered busy

and data transfer begins between a master and a slave. As

data is transferred over I2C in groups of nine bits (eight

data bits followed by an acknowledge bit), each group

takes nine SCL cycles. The transmitter releases the SDA

line during the acknowledge clock pulse and the receiver

issues an acknowledge (ACK) by pulling SDA low or leaves

SDA high to indicate a not acknowledge (NAK) condition.

Change of data state can only happen while SCL is low.

Write Protocol

The master begins a write operation with a START condi-

tion followed by the seven bit slave address 1100100

and the R/W bit set to zero, as shown in Figure 4. The

LTC2942 acknowledges this by pulling SDA low and then

the master sends a command byte which indicates which

internal register the master is to write. The LTC2942 ac-

knowledges and latches the command byte into its internal

the LTC2942 acknowledges once more and latches the

data into the desired register. The transmission is ended

when the master sends a STOP condition. If the master

continues by sending a second data byte instead of a stop,

the LTC2942 acknowledges again, increments its address

pointer and latches the second data byte in the following

Read Protocol

The master begins a read operation with a START condition

followed by the seven bit slave address 1100100 and the

R/W bit set to zero, as shown in Figure 6. The LTC2942

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

1 - 7

2942 F03

a6 - a0

b7 - b0

1 - 7

Figure 3. Data Transfer Over I2C or SMBus

FROM MASTER TO SLAVE

ADDRESS

DATA

FROM SLAVE TO MASTER

2942 F04

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

S: START CONDITION

P: STOP CONDITION

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

1100100

01h

FCh

Figure 4. Writing FCh to the LTC2942 Control Register (B)

ADDRESS

DATA

2942 F05

1100100

02h

F0h

01h

DATA

ADDRESS

2942 F06

ADDRESS

1100100

00h

1100100

01h

DATA

Figure 5. Writing F001h to the LTC2942

Accumulated Charge Register (C, D)

Figure 6. Reading the LTC2942 Status Register (A)

ADDRESS

2942 F07

ADDRESS

1100100

08h

1100100

F1h

DATA

24h

DATA

Figure 7. Reading the LTC2942 Voltage Register (I, J)

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