DM9010BEP datasheet(39/62 Pages) DAVICOM

39 / 62 page

DM9010B

Single Chip Ethernet Controller with General Processor Interface

Preliminary

Version: DM9010B--DS-P01

September 5, 2007

Writing a 1 to this bit will cause PHY entering the Sleep mode and

power down all circuit except oscillator and clock generator circuit.

When waking up from Sleep mode (write this bit to 0), the

configuration will go back to the state before sleep; but the state

machine will be reset

16.0

RLOUT

0, RW

Remote Loop out Control

When this bit is set to 1, the received data will loop out to the

transmit channel. This is useful for bit error rate testing

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17

Bit

Bit Name

Default

Description

17.15

100FDX

1, RO

100M Full Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit. If this

bit is 1, it means the operation 1 mode is a 100M full duplex mode. The

software can read bit [15:12] to see which mode is selected after

auto-negotiation. This bit is invalid when it is not in the auto-negotiation

mode

17.14

100HDX

1, RO

100M Half Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit. If this

bit is 1, it means the operation 1 mode is a 100M half duplex mode. The

software can read bit [15:12] to see which mode is selected after

auto-negotiation. This bit is invalid when it is not in the auto-negotiation

mode

17.13

10FDX

1, RO

10M Full Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit. If this

bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The

software can read bit [15:12] to see which mode is selected after

auto-negotiation. This bit is invalid when it is not in the auto-negotiation

mode

17.12

10HDX

1, RO

10M Half Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit. If this

bit is 1, it means the operation 1 mode is a 10M half duplex mode. The

software can read bit [15:12] to see which mode is selected after

auto-negotiation. This bit is invalid when it is not in the auto-negotiation

mode

17.11-17.

Reserved

0, RO

Reserved

Read as 0, ignore on write

17.8-17.4 PHYADR[4

:0]

1, RW

PHY Address Bit 4:0

The first PHY address bit transmitted or received is the MSB of the

address (bit 4). A station management entity connected to multiple PHY

entities must know the appropriate address of each PHY

17.3-17.0 ANMB[3:0]

0, RO

Auto-negotiation Monitor Bits

These bits are for debug only. The auto-negotiation status will be written to

these bits.

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