DM9000_09 datasheet(29/53 Pages) DAVICOM

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DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

Version: DM9000-DS-F03

April 23, 2009

0 = MF preamble suppression bit off

16.1

SLEEP

0, RW

Sleep Mode

Writing a 1 to this bit will cause PHY to enter the Sleep mode and

power down all circuit except oscillator and clock generator circuit.

When waking up from Sleep mode (write this bit to 0), the

configuration will go back to the state before sleep; but the state

machine will be reset

16.0

RLOUT

0, RW

Remote Loopout Control

When this bit is set to 1, the received data will loop out to the

transmit channel. This is useful for bit error rate testing

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17

Bit

Bit Name

Default

Description

17.15

100FDX

1, RO

100M Full Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit.

If this bit is 1, it means the operation 1 mode is a 100M full duplex

mode. The software can read bit[15:12] to see which mode is

selected after auto-negotiation. This bit is invalid when it is not in the

auto-negotiation mode

17.14

100HDX

1, RO

100M Half Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit.

If this bit is 1, it means the operation 1 mode is a 100M half duplex

mode. The software can read bit [15:12] to see which mode is

selected after auto-negotiation. This bit is invalid when it is not in the

auto-negotiation mode

17.13

10FDX

1, RO

10M Full Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit.

If this bit is 1, it means the operation 1 mode is a 10M Full Duplex

mode. The software can read bit [15:12] to see which mode is

selected after auto-negotiation. This bit is invalid when it is not in the

auto-negotiation mode

17.12

10HDX

1, RO

10M Half Duplex Operation Mode

After auto-negotiation is completed, results will be written to this bit.

If this bit is 1, it means the operation 1 mode is a 10M half duplex

mode. The software can read bit[15:12] to see which mode is

selected after auto-negotiation. This bit is invalid when it is not in the

auto-negotiation mode

17.11-17.

RESERVED

0, RO

Reserved

Write as 0, ignore on read

17.8-17.4 PHYADR[4:0]

(PHYADR),

PHY Address Bit 4:0

The first PHY address bit transmitted or received is the MSB of the

address (bit 4). A station management entity connected to multiple

PHY entities must know the appropriate address of each PHY

17.3-17.0

ANMB[3:0]

0, RO

Auto-negotiation Monitor Bits

These bits are for debug only. The auto-negotiation status will be

written to these bits

B3 b2 b1 b0

0000

In IDLE State

0001

Ability Match

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