PIC12F609-ESLASHP datasheet(61/212 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41302D-page 61

PIC12F609/615/617/12HV609/615

7.10

ECCP Special Event Trigger

(PIC12F615/617/HV615 only)

If a ECCP is configured to trigger a special event, the

trigger will clear the TMR1H:TMR1L register pair. This

special event does not cause a Timer1 interrupt. The

ECCP module may still be configured to generate a

ECCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L

Timer1.

Timer1 should be synchronized to the FOSC to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the ECCP, the write

will take precedence.

For more information, see Section 11.0 “Enhanced

Capture/Compare/PWM (With Auto-Shutdown and

Dead Band) Module (PIC12F615/617/HV615 only)”.

7.11

Comparator Synchronization

The same clock used to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comparator changes.

For more information, see Section 9.0 “Comparator

Module”.

FIGURE 7-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1:

Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of

the clock.

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