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AS1332

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Layout Considerations

The AS1332 converts higher input voltage to lower output voltage with high efficiency. This is achieved with an inductor

based switching topology. During the first half of the switching cycle, the internal PMOS switch turns on, the input

voltage is applied to the inductor, and the current flows from PVDD line to the output capacitor (C2) through the

inductor. During the second half cycle, the PMOS turns off and the internal NMOS turns on. The inductor current

continues to flow via the inductor from the device PGND line to the output capacitor (C2). Referring to Figure 32, the

AS1332 has two major current loops where pulse and ripple current flow. The loop shown in the left hand side is most

important, because pulse current shown in Figure 32 flows in this path. The right hand side is next. The current

waveform in this path is triangular, as shown in Figure 32. Pulse current has many high-frequency components due to

fast di/dt. Triangular ripple current also has wide high-frequency components. Board layout and circuit pattern design

of these two loops are the key factors for reducing noise radiation and stable operation. Other lines, such as from

battery to C1(+) and C2(+) to load, are almost DC current, so it is not necessary to take so much care. Only pattern

width (current capability) and DCR drop considerations are needed.

Figure 32. Current Loop

PGND

AGND

VCON

EN

PVIN

VDD

SW

FB

4.7 µF

3.3 µH

2.7V to 5.5V

10 µF

C1

+

-

C2

+

-

L1

i

fOSC = 2MHz

i

0.52V to 1.27V