PCF2129AT datasheet(30/68 Pages) NXP

30 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

30 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

8.10.3 Watchdog timer function

The watchdog timer function is enabled or disabled by the WD_CD bit of the register

Watchdg_tim_ctl (see Table 30).

The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock

frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1

⁄

60 Hz (see Table 32).

When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val

determines the watchdog timer period.

The watchdog timer counts down from the software programmed 8-bit binary value n in

(register Control_2) is set logic 1 and an interrupt will be generated.

The counter does not automatically reload.

When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU)

loads a watchdog timer value n, then:

• the flag WDTF is reset

• INT is cleared

• the watchdog timer starts again

Loading the counter with 0 will:

• reset the flag WDTF

• clear INT

• stop the watchdog timer

Remark: WDTF is read only. A read of the register Control_2 will automatically reset the

flag WDTF.

Table 32.

Programmable watchdog timer

TF[1:0]

Timer source

clock frequency

Units

Minimum timer

period (n = 1)

Units

Maximum timer

period (n = 255)

Units

4.096

kHz

244

μs

62.256

15.625

3.984

255

⁄

15300

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