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LPC1766 bảng dữ liệu(PDF) 36 Page - NXP Semiconductors |
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LPC1766 bảng dữ liệu(HTML) 36 Page - NXP Semiconductors |
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36 / 66 page ![]() LPC1769_68_67_66_65_64_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 1 February 2010 36 of 66 NXP Semiconductors LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller 7.30 System control 7.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.29.5), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 5. Power distribution REAL-TIME CLOCK BACKUP REGISTERS 3.3 V REGULATOR 32 kHz OSCILLATOR POWER SELECTOR ULTRA-LOW POWER REGULATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aad978 RTCX1 VBAT VDD(REG)(3V3) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VREFN VSSA LPC17xx |
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