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MPC8544EBVTARJ bảng dữ liệu(PDF) 30 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8544EBVTARJ
Giải thích chi tiết về linh kiện  PowerQUICC??III Integrated Processor Hardware Specifications
PDF  120 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8544EBVTARJ bảng dữ liệu(HTML) 30 Page - Freescale Semiconductor, Inc

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MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3
30
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 9. Receive Input Compliance Mask
Figure 10 provides the AC test load for SGMII.
Figure 10. SGMII AC Test/Measurement Load
8.5
FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this
section.
8.5.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performance and are described in a source-synchronous fashion like
FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
01
0.275
0.4
0.6
0.725
0
Vrx_diffpp_max/2
Vrx_diffpp_min/2
–Vrx_diffpp_min/2
–Vrx_diffpp_max/2
Time (UI)
TX
Silicon
+ Package
C = CTX
C = CTX
R = 50
Ω
R = 50
Ω
D+ Package
Pin
D– Package
Pin
D+ Package
Pin



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