HT95R24 datasheet(21/53 Pages) HOLTEK

21 / 53 page

HT95R24

Rev. 1.00

February 17, 2009

When the Timer/Event Counter is read or if data is writ-

ten to the preload registers, the clock is inhibited to

avoid errors, however as this may result in a counting er-

ror, this should be taken into account by the program-

mer. Care must be taken to ensure that the timers are

properly initialised before using them for the first time.

The associated timer enable bits in the interrupt control

terrupt associated with the timer will remain inactive.

The edge select, timer mode and clock source control

bits in timer control register must also be correctly set to

ensure the timer is properly configured for the required

application. It is also important to ensure that an initial

value is first loaded into the timer register before the

timer is switched on; this is because after power-on the

initial value of the timer register is unknown. After the

timer has been initialised the timer can be turned on and

off by controlling the enable bit in the timer control regis-

ter. Note that setting the timer enable bit high to turn the

timer on, should only be executed after the timer mode

bits have been properly setup. Setting the timer enable

bit high together with a mode bit modification, may lead

to improper timer operation if executed as a single timer

control register byte write instruction.

When the Timer/Event counter overflows, its corre-

sponding interrupt request flag in the interrupt control

will in turn generate an interrupt signal. However irre-

spective of whether the interrupts are enabled or not, a

Timer/Event counter overflow will also generate a

wake-up signal if the device is in a Power-down condi-

tion. This situation may occur if the Timer/Event Counter

is in the Event Counting Mode and if the external signal

continues to change state. In such a case, the

Timer/Event Counter will continue to count these exter-

nal events and if an overflow occurs the device will be

woken up from its Power-down condition. To prevent

such a wake-up from occurring, the timer interrupt re-

quest flag should first be set high before issuing the

HALT instruction to enter the Power Down Mode.

Timer Program Example

This program example shows how the Timer/Event

Counter registers are setup, along with how the inter-

rupts are enabled and managed. Note how the

Timer/Event Counter is turned on, by setting bit 4 of the

Timer Control Register. The Timer/Event Counter can

be turned off in a similar way by clearing the same bit.

This example program sets the Timer/Event Counter tobe in the timer mode, which uses the internal system clock as

the clock source.

Org 04h

; external interrupt vector

reti

Org 08h

; Timer/Event Counter 0 interrupt vector

jmp tmr0nt

; jump here when Timer 0 overflows

org 20h

; main program

;internal Timer/Event Counter interrupt routine

tmr0nt:

; Timer/Event Counter main program placed here

reti

begin:

;setup Timer registers

mov a,01fh

; setup preload value

- timer counts from this value to FFFFH

mov tmr01,a

mov a,09bh

mov tmr0h,a

mov a,080h

; setup Timer control register

mov tmr0c,a

; timer mode

; setup interrupt register

mov a,005h

; enable master interrupt and timer interrupt

mov intc0,a

set tmrc0.4

; start Timer

- note mode bits must be previously setup

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