MCF5271 datasheet(21/42 Pages) FREESCALE

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Electrical Characteristics

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

XTAL Load Capacitance5

530

PLL Lock Time 5, 7,13

tlpll

—750

μs

Power-up To Lock Time 5, 6,8

With Crystal Reference (includes 5 time)

Without Crystal Reference9

tlplk

—

750

μs

1:1 Mode Clock Skew (between CLKOUT

and EXTAL) 10

tskew

–1

Duty Cycle of reference 5

tdc

Frequency un-LOCK Range

fUL

–3.8

4.1

% fsys/2

Frequency LOCK Range

fLCK

–1.7

2.0

% fsys/2

CLKOUT Period Jitter, 5, 6, 8,11, 12

Measured at fsys/2 Max

Peak-to-peak Jitter (Clock edge to clock

edge)

Long Term Jitter (Averaged over 2 ms

interval)

Cjitter

—

5.0

.01

% fsys/2

Frequency Modulation Range Limit13,14

(fsys/2 Max must not be exceeded)

Cmod

0.8

2.2

%fsys/2

ICO Frequency. fico = fref × 2 × (MFD+2)

fico

150

MHz

All values given are initial design targets and subject to change.

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL

into self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls

below fLOR with default MFD/RFD settings.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This specification applies to the period required for the PLL to relock after changing the MFD frequency

control bits in the synthesizer control register (SYNCR).

Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are

valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the

crystal start up time must be added to the PLL lock time to determine the total start-up time.

tlpll = (64 * 4 * 5 + 5 τ) Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10

-6 2(MFD +

2).

10 PLL is operating in 1:1 PLL mode.

11 Jitter is the average deviation from the programmed frequency measured over the specified interval at

maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a

stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in

crystal oscillator frequency increase the Cjitter percentage for a given interval.

12 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of

Cjitter+Cmod.

13 Modulation percentage applies over an interval of 10

μs, or equivalently the modulation rate is 100KHz.

14 Modulation rate selected must not result in f

sys/2 value greater than the fsys/2 maximum specified value.

Modulation range determined by hardware design.

15 f

sys/2 = fico / (2 * 2

RFD)

Table 10. HiP7 PLLMRFM Electrical Specifications1 (continued)

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

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