TS2DDR2811 datasheet(6/13 Pages) TI

6 / 13 page

(see Note A)

TEST CIRCUIT

2 × VCC

Open

GND

50 Ω

VG1

VCC

DUT

50 Ω

VSEL

50 Ω

VG2

50 Ω

TEST

V∆

VCC

tPLZ/tPZL

3.3 V ± 0.3 V

2 × VCC

200 Ω

GND

10 pF

0.3 V

Input Generator

tPHZ/tPZH

3.3 V ± 0.3 V

GND

200 Ω

VCC

10 pF

0.3 V

tPZL

VOH - 0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

Output Control

)

(VSEL

1.65 V

3.3 V

VOH

VOL + 0.3 V

VOH

VOL

0 V

1.65 V

tPZH

tPLZ

tPHZ

Output

Waveform 2

S1 at GND

(see Note B)

Output

Waveform 1

S1 at 2 × VCC

(see Note B)

VOL

VSEL

TS2DDR2811

SCDS294 – DECEMBER 2009

www.ti.com

PARAMETER MEASUREMENT INFORMATION

(Enable and Disable Times)

CL includes probe and jig capacitance.

Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output

control. Waveform 2is for an output with internal conditions such that the output is high, except when disabled by the

output control.

All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5

ns, tf ≤ 2.5 ns.

The outputs are measured one at a time, with one transition per measurement.

tPLZ and tPHZ are the same as tdis.

tPZL and tPZH are the same as ten.

Figure 5. Test Circuit and Voltage Waveforms

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