1

3

4

5

6

7

8

9

10

11

12

2

25

26

27

28

29

30

31

32

33

34

35

36

NC

VCC

2A

2B

NC

GND

GND

NC

3A

3B

VCC

NC

1R

NC

GND

2R

NC

GND

PDN

3R

NC

GND

4R

NC

SN65MLVD048

SLLS903 – DECEMBER 2009

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

NO.

1R––4R

36, 33, 29, 26

O

Data output from receivers

1A–4A

47, 3, 9, 13

I/O

M-LVDS bus non-inverting input/output

1B–4B

48, 4, 10, 14

I/O

M-LVDS bus inverting input/output

6, 7, 18, 23, 27, 31,

GND

I

Circuit ground. ALL GND pins must be connected to ground.

34, 38, 43

2, 11, 15, 16, 24, 37,

I

Supply voltage. ALL VCC pins must be connected to supply.

45, 46

Receiver enable, active low, enables individual receivers. When this pin is left floating,

1RE–4RE

40, 42, 19, 21

I

internally this pin will be pulled to logic HIGH.

Failsafe enable pin. When this pin is left floating, internally this pin will be pulled to logic

HIGH.

This pin enables the Type 2 receiver for the respective channel.

1FSEN–4FSEN

39, 41, 20, 22

I

xFSEN = L

→ Type 1 receiver inputs

xFSEN = H

→ Type 2 receiver inputs

Power Down pin. When this pin is left floating, internally this pin will be pulled to logic LOW.

When PDN is HIGH, the device is powered up.

PDN

30

When PDN is LOW, the device overrides all other control and powers down. All outputs are

Hi-Z

1, 5, 8, 12, 17, 25, 28,

NC

Not Connected

32, 35

NC

44

Not Connected. Internal TI Test pin. This pin must be left unconnected.

PowerPAD™

–

Connected to GND

RGZ PACKAGE

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