BQ20Z45-R1DBTR datasheet(9/18 Pages) TI

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bq20z45-R1

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SLUS992 – DECEMBER 2009

DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND

SUPPLY VOLTAGE

Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Data retention

Years

Flash programming write-cycles

20k

Cycles

t(ROWPROG)

Row programming time

See (1)

t(MASSERASE) Mass-erase time

200

t(PAGEERASE) Page-erase time

I(DDPROG)

Flash-write supply current

I(DDERASE)

Flash-erase supply current

RAM BACKUP

V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 85°C

1000

2500

I(RB)

RB data-retention input current

V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 25°C

220

V(RB)

RB data-retention input voltage(1)

1.7

(1)

Specified by design. Not production tested.

SMBus TIMING CHARACTERISTICS

TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(SMB)

SMBus operating frequency

Slave mode, SMBC 50% duty cycle

100

kHz

Master mode, No clock low slave

f(MAS)

SMBus master clock frequency

51.2

kHz

extend

Bus free time between start and stop

t(BUF)

4.7

µs

(see Figure 1)

t(HD:STA)

Hold time after (repeated) start (see Figure 1)

µs

t(SU:STA)

Repeated start setup time (see Figure 1)

4.7

µs

t(SU:STO)

Stop setup time (see Figure 1)

µs

Receive mode

t(HD:DAT)

Data hold time (see Figure 1)

Transmit mode

300

t(SU:DAT)

Data setup time (see Figure 1)

250

t(TIMEOUT)

Error signal/detect (see Figure 1)

See (1)

µs

t(LOW)

Clock low period (see Figure 1)

4.7

µs

t(HIGH)

Clock high period (see Figure 1)

See (2)

µs

t(LOW:SEXT)

Cumulative clock low slave extend time

See (3)

Cumulative clock low master extend time

t(LOW:MEXT)

See (4)

(see Figure 1)

Clock/data fall time

See (5)

300

Clock/data rise time

See (6)

1000

(1)

The bq20z45-R1 times out when any clock low exceeds t(TIMEOUT).

(2)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z45-R1 that

is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).

(3)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4)

t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)

(6)

Fall time tf = 0.9VDD to (VILMAX – 0.15)

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