ATtiny261A datasheet(24/292 Pages) ATMEL

24 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

6. Clock System

Figure 6-1 presents the principal clock systems and their distribution. All of the clocks need not

be active at a given time. In order to reduce power consumption, the clocks to modules not being

used can be halted by using different sleep modes, as described in “Power Management and

Sleep Modes” on page 34.

Figure 6-1.

Clock Distribution

6.1

Clock Subsystems

The clock subsystems are detailed in the sections below.

6.1.1

CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

6.1.2

I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

General I/O

Modules

CPU Core

RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Calibrated RC

Oscillator

ADC

clk

ADC

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

System Clock

Prescaler

PLL

Oscillator

clk

PCK

General I/O

Modules

External Clock

clk

PLL

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