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ATtiny261A bảng dữ liệu(PDF) 159 Page - ATMEL Corporation |
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ATtiny261A bảng dữ liệu(HTML) 159 Page - ATMEL Corporation |
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159 / 292 page ![]() 159 8197A–AVR–10/09 ATtiny261A/461A/861A trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set . 15.13.5 DIDR0 – Digital Input Disable Register 0 • Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis- abled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. • Bit 3 – AREFD: AREF Digital Input Disable When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre- sponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the AREF pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 15.13.6 DIDR1 – Digital Input Disable Register 1 • Bits 7:4 – ADC10D:ADC7D: ADC10:7 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis- abled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC10:7 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Table 15-6. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter0 Compare Match A 1 0 0 Timer/Counter0 Overflow 1 0 1 Timer/Counter0 Compare Match B 1 1 0 Timer/Counter1 Overflow 1 1 1 Watchdog Interrupt Request Bit 7654 3 2 10 0x01 (0x21) ADC6D ADC5D ADC4D ADC3D AREFD ADC2D ADC1D ADC0D DIDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 0 0 00 Bit 7 65 432 10 0x02 (0x22) ADC10D ADC9D ADC8D ADC7D - DIDR1 Read/Write R/WR/W R/WR/W R R R R Initial Value 0 0 0 0 0 0 0 0 |
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