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ATtiny261A bảng dữ liệu(PDF) 103 Page - ATMEL Corporation |
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ATtiny261A bảng dữ liệu(HTML) 103 Page - ATMEL Corporation |
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103 / 292 page ![]() 103 8197A–AVR–10/09 ATtiny261A/461A/861A Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from the Dead Time Generator if either of the COM1x1:0 bits are set. The Output Compare pins can also be overriden by the Output Compare Override Enable bits OC1OE5:OC1OE0. If an Over- ride Enable bit is cleared, the actual value from the port register will be visible on the port pin and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on the port pin. The Output Compare Pin configurations are described in Table 12-5, Table 12-6 and Table 12-7. Table 12-5. Configuration of Output Compare Pins OC1A and OC1A in PWM6 Mode COM1A1 COM1A0 OC1A Pin (PB0) OC1A Pin (PB1) 0 0 Disconnected Disconnected 01OC1A • OC1OE0 OC1A • OC1OE1 10OC1A • OC1OE0 OC1A • OC1OE1 11OC1A • OC1OE0 OC1A • OC1OE1 Table 12-6. Configuration of Output Compare Pins OC1B and OC1B in PWM6 Mode COM1B1 COM1B0 OC1B Pin (PB2) OC1B Pin (PB3) 0 0 Disconnected Disconnected 01OC1A • OC1OE2 OC1A • OC1OE3 10OC1A • OC1OE2 OC1A • OC1OE3 11OC1A • OC1OE2 OC1A • OC1OE3 TCNT1 OC1A Pin OC1A Pin OC1B Pin OC1B Pin OC1D Pin OC1D Pin OC1OE0 OC1OE1 OC1OE2 OC1OE3 OC1OE4 OC1OE5 OCW1A |
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