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ATmega16A bảng dữ liệu(PDF) 132 Page - ATMEL Corporation |
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ATmega16A bảng dữ liệu(HTML) 132 Page - ATMEL Corporation |
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132 / 352 page ![]() 132 8154B–AVR–07/09 ATmega16A Table 17-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 123 for more details. Table 17-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor- rect PWM mode . Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 124 for more details. • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 17-6. Table 17-4. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 01 Reserved 1 0 Clear OC2 on compare match, set OC2 at BOTTOM, (non-inverting mode) 1 1 Set OC2 on compare match, clear OC2 at BOTTOM, (inverting mode) Table 17-5. Compare Output Mode, Phase Correct PWM Mode (1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 01 Reserved 1 0 Clear OC2 on compare match when up-counting. Set OC2 on compare match when downcounting. 1 1 Set OC2 on compare match when up-counting. Clear OC2 on compare match when downcounting. Table 17-6. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 00 1 clk T2S/(No prescaling) 01 0 clk T2S/8 (From prescaler) 01 1 clk T2S/32 (From prescaler) 10 0 clk T2S/64 (From prescaler) 10 1 clk T2S/128 (From prescaler) 11 0 clkT2S/256 (From prescaler) 11 1 clkT2S/1024 (From prescaler) |
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