ATmega16A datasheet(128/352 Pages) ATMEL

128 / 352 page

128

8154B–AVR–07/09

ATmega16A

Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-

caler (f

clk_I/O/8)

17.9

Asynchronous Operation of the Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe

procedure for switching clock source is:

Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.

Select clock source by setting AS2 as appropriate.

Write new values to TCNT2, OCR2, and TCCR2.

To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.

Clear the Timer/Counter2 Interrupt Flags.

Enable interrupts, if needed.

• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external

clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main

clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not

write a new value before the contents of the temporary register have been transferred to its

destination. Each of the three mentioned registers have their individual temporary register,

which means for example that writing to TCNT2 does not disturb an OCR2 write in progress.

To detect that a transfer to the destination register has taken place, the Asynchronous Status

• When entering Power-save or Extended Standby mode after having written to TCNT2,

OCR2, or TCCR2, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if the Output Compare2

interrupt is used to wake up the device, since the output compare function is disabled during

writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode

before the OCR2UB bit returns to zero, the device will never receive a compare match

interrupt, and the MCU will not wake up.

OCFn

OCRn

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

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