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ATtiny13A-SSH bảng dữ liệu(PDF) 94 Page - ATMEL Corporation

tên linh kiện ATtiny13A-SSH
Giải thích chi tiết về linh kiện  8-bit Microcontroller with 1K Bytes In-System Programmable Flash
PDF  174 Pages
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ATtiny13A-SSH bảng dữ liệu(HTML) 94 Page - ATMEL Corporation

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8126D–AVR–11/09
ATtiny13A
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
14.12.3
ADCL and ADCH – The ADC Data Register
14.12.3.1
ADLAR = 0
14.12.3.2
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
Table 14-4.
ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
000
2
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Bit
151413121110
9
8
0x05
––––––
ADC9
ADC8
ADCH
0x04
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
76543210
Read/Write
RRRRRRRR
RRRRRRRR
Initial Value
00000000
00000000
Bit
151413121110
9
8
0x05
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
0x04
ADC1
ADC0
––––––
ADCL
76543210
Read/Write
RRRRRRRR
RRRRRRRR
Initial Value
00000000
00000000



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