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ATmega16HVB bảng dữ liệu(PDF) 188 Page - ATMEL Corporation |
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ATmega16HVB bảng dữ liệu(HTML) 188 Page - ATMEL Corporation |
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188 / 273 page ![]() 188 8042A–AVR–07/09 ATmega16HVB/32HVB • Bit 6 - TWBCIE: TWI Bus Connect/Disconnect Interrupt Enable When the TWBCIE bit and the I-bit in the Status Register are set, the TWI Bus Connect/Discon- ne ct In terr upt is e nab le d. Th e corre spon ding inte rrup t is execu t ed if a TWI Bus Connect/Disconnect occurs, i.e., when the TWBCIE bit is set. • Bit 5:3 - Res: Reserved Bits These bits are reserved bits in the ATmega16HVB/32HVB and will always read as zero. • Bit 2:1 - TWBDT1, TWBDT0: TWI Bus Disconnect Time-out Period The TWBDT bits decides how long both the TWI data (SDA) and clock (SCL) signals must be low before generating the TWI Bus Disconnect Interrupt. The different configuration values and their corresponding time-out periods are shown in Table 27-8. • Bit 0 - TWBCIP: TWI Bus Connect/Disconnect Interrupt Polarity The TWBCIP bit decide if the TWI Bus Connect/Disconnect Interrupt Flag (TWBCIF) should be set on a Bus Connect or a Bus Disconnect. If TWBCIP is cleared, the TWBCIF flag is set on a Bus Connect. If TWBCIP is set, the TWBCIF flag is set on a Bus Disconnect. Table 27-8. TW Bus Disconnect Time-out Period TWBDT1 TWBDT0 TWI Bus Disconnect Time-out Period 0 0 250 ms 0 1 500 ms 1 0 1000 ms 1 1 2000 ms |
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