ATmega16HVB datasheet(81/273 Pages) ATMEL

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8042A–AVR–07/09

ATmega16HVB/32HVB

16.3

16.3.1

TCCRnB – Timer/Counter n Control Register B

• Bits 2, 1, 0 – CSn2, CSn1, CSn0: Clock Select0, Bit 2, 1, and 0

The Clock Select n bits 2, 1, and 0 define the prescaling source of Timer n.

If external pin modes are used for the Timer/Counter n, transitions on the Tn pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

16.3.2

General Timer/Counter Control Register – GTCCR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler

reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can

be configured to the same value without the risk of one of them advancing during configuration.

When the TSM bit is written to zero the PSRSYNC bit is cleared by hardware, and the

Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-

mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1

and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

Bit

43210

(0x80)(0x81)

CSn2

CSn1

CSn0

TCCRnB

Read/Write

R/W

Initial Value

00000

Table 16-1.

Clock Select Bit Description

CSn2

CSn1

CSn0

Description

No clock source (Timer/Counter stopped)

001

clkI/O/(No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

101

clkI/O/1024 (From prescaler)

External clock source on Tn pin. Clock on falling edge.

External clock source on Tn pin. Clock on rising edge.

Bit

6543

0x23 (0x43)

TSM

–

PSRSYNC

GTCCR

Read/Write

R/W

RRRRRR

R/W

Initial Value

0000

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