ATmega16HVB datasheet(127/273 Pages) ATMEL

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127

8042A–AVR–07/09

ATmega16HVB/32HVB

Figure 21-2.

21.6.3

BGCSR - Bandgap control and Status Register

• Bits 7:6 - Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 5 -BGD: Bandgap Disable

Setting this bit to one will disable the bandgap voltage reference. This bit must be cleared (zero)

before enabling Cell Balancing, CC-ADC, V-ADC or Battery Protection, and must remain unset

(zero) while either of these modules are enabled. Note that after clearing this bit, a settling time

is required before the voltage is stable, see ”Bandgap Buffer Settling Time” on page 125.

• Bit 4 - BGSCDE: Bandgap Short Circuit Detection Enabled

Setting this bit to one will enable the bandgap Short Circuit Detector. This bit should be cleared if

the BGD bit in the BGCSR is set to one to avoid false setting of the BGSCDIF bit.

• Bits 3:2 - Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 1 - BGSCDIF: Bandgap Short Circuit Detection Interrupt Flag

The bit is set when the Bandgap Short Circuit Detector is enabled and buffered bandgap refer-

ence is different from the unbuffered Bandgap reference. The BGSCDIF is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, BGSCDIF is cleared

by writing a logic one to its bit position.

Bit

(0xD2)

BGD

BGSCDE

BGSCDIF

BGSCDIE

BGCSR

Read/Write

R/W

Initial Value

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