ATmega169P datasheet(133/393 Pages) ATMEL

133 / 393 page

133

8018N–AVR–08/09

ATmega169P

15.11.7

ICR1H and ICR1L – Input Capture Register 1

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See ”Accessing 16-bit Registers” on page 109.

15.11.8

TIMSK1 – Timer/Counter1 Interrupt Mask Register

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See ”Interrupts” on page 56.) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (See ”Interrupts” on page 56.) is executed when the OCF1B Flag, located in

TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (See ”Interrupts” on page 56.) is executed when the OCF1A Flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See ”Interrupts” on page 56.) is executed when the TOV1 Flag, located in TIFR1, is set.

Bit

765

432

(0x87)

ICR1[15:8]

ICR1H

(0x86)

ICR1[7:0]

ICR1L

Read/Write

R/W

Initial Value

Bit

765

(0x6F)

–

–ICIE1

–

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

R/W

Initial Value

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