M16CSLASH56D datasheet(19/85 Pages) RENESAS

19 / 85 page

REJ03B0307-0110 Rev.1.10 Dec 01, 2009

Page 19 of 83

M16C/5LD Group, M16C/56D Group

2. Central Processing Unit (CPU)

Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen

configure a register bank. There are two sets of register banks.

Figure 2.1

Central Processing Unit Registers

R0H(high-order bitsof R0)

b15

b8 b7

INTBH

USP

ISP

Note:

1. These registers configure a register bank. There are two register banks.

IPL

b31

b19

INTBL

b15

INTBH is the 4 high-order bits of INTB register and

INTBL is the 16 low-order bits

b19

b15

FLG

b15

Data registers (1)

Address registers (1)

Frame base registers (1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

R1H(high-order bitsof R1)

R0L(low-order bitsof R0)

R1L(low-order bitsof R1)

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