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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ATmega328P bảng dữ liệu(PDF) 290 Page - ATMEL Corporation |
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ATmega328P bảng dữ liệu(HTML) 290 Page - ATMEL Corporation |
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290 / 345 page  290 7810A–AVR–11/09 ATmega328P [Preliminary] 27.5 Page Size 27.6 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega328P. Pulses are assumed to be at least 250 ns unless otherwise noted. 27.6.1 Signal Names In this section, some pins of the ATmega328P are referenced by signal names describing their functionality during parallel programming, see Figure 27-1 and Table 27-11. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 27-13. When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 27-14. Figure 27-1. Parallel Programming Note: V CC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V Table 27-9. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATmega328P 16K words (32K bytes) 64 words PC[5:0] 256 PC[13:6] 13 Table 27-10. No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB ATmega328P 1K bytes 4 bytes EEA[1:0] 256 EEA[9:2] 9 VCC GND XTAL1 PD1 PD2 PD3 PD4 PD5 PD6 PC[1:0]:PB[5:0] DATA RESET PD7 +12 V BS1 XA0 XA1 OE RDY/BSY PAGEL PC2 WR BS2 AVCC +4.5 - 5.5V +4.5 - 5.5V |
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