ATmega328P datasheet(191/345 Pages) ATMEL

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191

7810A–AVR–11/09

ATmega328P [Preliminary]

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

19.10.5

UBRRnL and UBRRnH – USART Baud Rate Registers

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRnH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four

most significant bits, and the UBRRnL contains the eight least significant bits of the USART

baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud

rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.

Table 19-7.

UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

5-bit

6-bit

7-bit

8-bit

Reserved

9-bit

Table 19-8.

UCPOLn Bit Settings

UCPOLn

Transmitted Data Changed (Output of

TxDn Pin)

Received Data Sampled (Input on RxDn

Pin)

Rising XCKn Edge

Falling XCKn Edge

Rising XCKn Edge

Bit

151413

1211

–

UBRRn[11:8]

UBRRnH

UBRRn[7:0]

UBRRnL

Read/Write

R/W

Initial Value

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