ATmega328P datasheet(172/345 Pages) ATMEL

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7810A–AVR–11/09

ATmega328P [Preliminary]

A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 19-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 19-4. Frame Formats

Start bit, always low.

(n)

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

IDLE

No transfers on the communication line (RxDn or TxDn). An IDLE line

must be high.

The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in

UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores

the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the

first stop bit is zero.

19.4.1

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

even

Parity bit using even parity

Podd

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

[5]

[6]

[7]

[8]

[P]

Sp1 [Sp2]

(St / IDLE)

(IDLE)

FRAME

Peven

dn 1

–

… d

Podd

⊕ ⊕

⊕⊕⊕⊕

dn 1

–

… d

⊕ ⊕

⊕⊕⊕⊕

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