ATtiny45 datasheet(94/196 Pages) ATMEL

94 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

The length of the counting period is user adjustable by selecting the dead time prescaler setting

in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register

consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM

output and its’ complementary output separately. Thus the rising edge of OC1x and

OC1x can

have different dead time periods. The dead time is adjusted as the number of prescaled dead

time generator clock cycles.

Figure 15-3. The Complementary Output Pair

15.1

Timer/Counter1 Dead Time Prescaler register 1 - DTPS1

The dead time prescaler register, DTPS1 is a 2-bit read/write register.

Bits 1 - 0 - DTPS1: Timer/Counter1 Dead Time Prescaler register 1

The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the

Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can

be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead

Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The

division factors are given in table 46..

OC1x

x = A or B

t non-overlap / rising edge

t non-overlap / falling edge

OC1x

PWM1x

Bit

765

43210

$23 ($43)

DTPS11

DTPS10

DTPS1

Read/Write

RRRRRR

R/W

Initial value

000

00000

Table 15-1.

Division factors of the Dead Time prescaler

DTPS11

DTPS10

Prescaler divides the T/C1 clock by

1x (no division)

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