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R5F64111DFB bảng dữ liệu(PDF) 73 Page - Renesas Technology Corp |
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R5F64111DFB bảng dữ liệu(HTML) 73 Page - Renesas Technology Corp |
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73 / 105 page ![]() REJ03B0227-0110 Rev.1.10 Sep 17, 2009 Page 73 of 99 R32C/111 Group 5. Electrical Characteristics VCC1 =VCC2 =5V Note: 1. Pins AN0_4 to AN0_7, ANEX0, and ANEX1 are available in the 100- and 80-pin package only. Table 5.18 A/D Conversion Characteristics (VCC1 =VCC2 =AVCC =VREF = 4.2 to 5.5 V, VSS =AVSS =0 V, Ta =Topr, and f(BCLK) = 25 MHz, unless otherwise noted) Symbol Characteristic Measurement condition Value Unit Min. Typ. Max. — Resolution VREF = VCC1 10 Bits — Absolute error VREF = VCC1 = VCC2 = 5 V AN_0 to AN_7, AN0_0toAN0_7, AN2_0toAN2_7, ANEX0, ANEX1 (1) ±3 LSB External op-amp connection mode ±7 LSB INL Integral non-linearity error VREF = VCC1 = VCC2 = 5 V AN_0 to AN_7, AN0_0toAN0_7, AN2_0toAN2_7, ANEX0, ANEX1 (1) ±3 LSB External op-amp connection mode ±7 LSB DNL Differential non-linearity error ±1 LSB —Offset error ±3 LSB — Gain error ±3 LSB RLADDER Resistor ladder VREF = VCC1 420 k Ω tCONV Conversion time (10 bits) φ AD = 16 MHz, with sample and hold function 2.06 µs φ AD = 16 MHz, without sample and hold function 3.69 µs tCONV Conversion time (8 bits) φ AD = 16 MHz, with sample and hold function 1.75 µs φ AD = 16 MHz, without sample and hold function 3.06 µs tSAMP Sample time φ AD = 16 MHz 0.188 µs VIA Analog input voltage 0 VREF V φ AD Operating clock frequency without sample and hold function 0.25 16 MHz with sample and hold function 1 16 MHz |
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