R5F64110DFB datasheet(68/105 Pages) RENESAS

68 / 105 page

REJ03B0227-0110 Rev.1.10 Sep 17, 2009

Page 68 of 99

R32C/111 Group

5. Electrical Characteristics

Note:

This value is applicable only when the main clock oscillation is stable.

Note:

This recovery time does not include the period until the main clock oscillator is stabilized. The CPU

starts operating before the oscillator is stabilized.

Figure 5.4

Clock Circuit Timing

Table 5.12

Electrical Characteristics of Oscillator

(VCC1 =VCC2 = 3.0 to 5.5 V, VSS =0 V, and Ta =Topr, unless otherwise noted)

Symbol

Characteristics

Measurement

condition

Value

Unit

Min.

Typ.

Max.

fSO(PLL)

PLL clock self-oscillation frequency

MHz

tLOCK(PLL)

PLL lock time (1)

1ms

tjitter(p-p)

PLL jitter period (p-p)

2.0

f(OCO)

On-chip oscillator frequency

62.5

125

250

kHz

Table 5.13

Electrical Characteristics of Clock Circuitry

(VCC1 =VCC2 = 3.0 to 5.5 V, VSS =0 V, and Ta =Topr, unless otherwise noted)

Symbol

Characteristics

Measurement

condition

Value

Unit

Min.

Typ.

Max.

trec(STOP) Recovery time from stop mode (1)

225

µs

trec(WAIT)

Recovery time from wait mode to low power mode

225

µs

t rec(STOP)

Interrupt for exiting

stop mode

Recovery time from stop mode

t rec(STOP)

CPU clock

Main clock oscillator

output

On-chip oscillator

output

t rec(WAIT)

Interrupt for exiting

wait mode

Sub clock oscillator

output

Recovery time from wait mode

to low power mode

t rec(WAIT)

CPU clock

On-chip oscillator

output

R5F64110DFB bảng dữ liệu(PDF) 68 Page - Renesas Technology Corp

R5F64110DFB bảng dữ liệu(HTML) 68 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL