4

6483A–ATARM–04-Aug-09

ATSAM3U Errata

1.2.5

Power Management Controller (PMC)

1.2.5.1

PMC: SysTick does not work properly if MCK/8 is selected as clock source

and is configured by the CLKSOURCE bit of the SysTick CTRL register.

When setting CLKSOURCE to 0 (MCK/8), SysTick does not work properly.

Workaround

Set CLKSOURCE at 1 (MCK selected as SysTick source).

Problem Fix

This issue will be fixed in the next revision.

1.2.5.2

PMC: Main Oscillator Crystal Failure detection not functional

When the 32768 Hz Crystal Oscillator is selected as slow clock source and if the Main Oscillator

Crystal Failure detection is enabled, the CFDEV, CFDS and FOS status bits in the PMC_SR

register do not rise.

Workaround

Use the Embedded 32 kHz RC Oscillator as slow clock source.

Problem Fix

This issue will be fixed in the next revision.

1.2.5.3

PMC: Main Oscillator Frequency selection if the Main On Chip RC Oscillator is off

When the 4/8/12 MHz RC Oscillator is off, the frequency selection (MOSCRCF in CKGR_MOR)

can not be changed. The register can be written but the modification on MOSCRCF will not be

taken into account.

Workaround

Modify MOSCRCF when the 4/8/12 MHz RC Oscillator is on (MOSCRCEN =1).

Problem Fix

This issue will be fixed in the next revision.

1.2.6

SAM3U Matrix (MATRIX)

1.2.6.1

MATRIX: I/D default master for Flash after reset

The I/D Cortex-M3 bus is not set as default master for the Flash after reset. There is a minor

impact in terms of performance when running the code from the Flash (about 5%).

Workaround

Configure by software the I/D Cortex-M3 bus as default Master for the Flash.

Problem Fix

This issue will be fixed in the next revision.

1.2.7

PIO

1.2.7.1

PIO: NCS1 on PA16

The chip select 1 (NCS1) of the SMC on PA16 (Peripheral B) does not work.

Workaround