AT89LP213 datasheet(73/98 Pages) ATMEL

73 / 98 page

3538D–MICRO–10/09

AT89LP213/214

23.8

Programming Interface Timing

This section details general system timing sequences and constraints for entering or exiting In-

System Programming as well as parameters related to the Serial Peripheral Interface during

ISP. The general timing parameters for the following waveform figures are listed in Section

23.8.6 “Timing Parameters” on page 76.

23.8.1

Power-up Sequence

Execute this sequence to enter programming mode immediately after power-up. In the RST pin

is disabled or if the ISP Fuse is disabled, this is the only method to enter programming (see Sec-

tion 10.3 “External Reset” on page 16).

Apply power between VCC and GND pins. RST should remain low.

Wait at least t

PWRUP. and drive SS high.

Wait at least t

SUT for the internal Power-on Reset to complete. The value of tSUT will

depend on the current settings of the device.

Start programming session.

Figure 23-5. Serial Programming Power-up Sequence

23.8.2

Power-down Sequence

Execute this sequence to power-down the device after programming.

Drive SCK low.

Wait at least t

SSD and bring SS high.

Tristate MOSI.

Wait at least t

SSZ and then tristate SS and SCK.

Wait no more than t

PWRDN and power off VCC.

Figure 23-6. Serial Programming Power-down Sequence

VCC

RST

SCK

HIGH Z

MISO

HIGH Z

MOSI

tPWRUP

tPOR + tSUT

tZSS

VCC

RST

SCK

HIGH Z

MISO

HIGH Z

MOSI

tPWRDN

tSSD

tSSZ

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