12

AT88SC25616C

5017KS–SMEM–08/09

11.

Security Options

11.1.

Anti-tearing

In the event of a power loss during a write cycle, the integrity of the device’s stored data may be recovered. This

function is optional: the host may choose to activate the anti-tearing function, depending on application requirements.

When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete

them, and data are limited to eight bytes.

Data are written first to a buffer zone in EEPROM instead of the intended destination address, but with the same

access conditions. The data are then written in the required location. If this second write cycle is interrupted due to a

power loss, the device will automatically recover the data from the system buffer zone at the next power-up.

In 2-wire mode, the host is required to perform ACK polling for up to 8 ms after write commands when anti-tearing is

active. At power-up, the host is required to perform ACK polling, in some cases for up to 2 ms, in the event that the

device needs to carry out the data recovery process.

11.2.

Write Lock

If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access

byte for the bytes of that page.

Example

The write lock byte at $080 controls the bytes from $080 to $087.

Figure 12.

Write Lock Example

Address

$0

$1

$2

$3

$4

$5

$6

$7

$080

11011001 xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

locked

locked

locked

The write lock byte may also be locked by writing its least significant (rightmost) bit to “0”. Moreover, when write lock

mode is activated, the write lock byte can only be programmed – that is, bits written to “0” cannot return to “1”.

In the write lock configuration, only one byte can be written at a time. Even if several bytes are received, only the first

byte will be taken into account by the device.