AT91SAM9G45 datasheet(39/54 Pages) ATMEL

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6438CS–ATARM–13-Oct-09

AT91SAM9G45

9.3

Peripheral Interrupts and Clock Control

9.3.1

System Interrupt

The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:

• the DDR2/LPDDR Controller

• the Debug Unit

• the Periodic Interval Timer

• the Real-Time Timer

• the Real-Time Clock

• the Watchdog Timer

• the Reset Controller

• the Power Management Controller

The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used

within the Advanced Interrupt Controller.

9.3.2

External Interrupts

All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a

dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.

9.4

Peripheral Signals Multiplexing on I/O Lines

The AT91SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which mul-

tiplexes the I/O lines of the peripheral set.

Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral

functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of

the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and

“Comments” have been inserted in this table for the user’s own comments; they may be used to

track how pins are defined in an application.

Note that some peripheral function which are output only, might be duplicated within the both

tables.

The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral

mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the

device is maintained in a static state as soon as the reset is released. As a result, the bit corre-

sponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.

If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-

tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling

memories, in particular the address lines, which require the pin to be driven as soon as the reset

is released. Note that the pull-up resistor is also enabled in this case.

To amend EMC, programmable delay has been inserted on PIO lines able to run at high speed.

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