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ICS853S024 bảng dữ liệu(PDF) 11 Page - Integrated Device Technology

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Giải thích chi tiết về linh kiện  LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
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ICS853S024
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
PRELIMINARY
LOW SKEW LVPECL FANOUT BUFFER
11
ICS853S024AY REV. A APRIL 30, 2008
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S024.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS853S024 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 200mA = 693mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 24 * 30mW = 720mW
Total Power_MAX (3.465V, with all outputs switching) = 693W + 720mW = 1.413W
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming 0 air flow
and a multi-layer board, the appropriate value is 32.5°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.413 W * 32.5°C/W = 115.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5. Thermal Resistance θJA for 64 Lead TQFP, EPad, Forced Convection
θ
JA by Velocity
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.5°C/W
26.6°C/W
25.1°C/W



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