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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PCIMX513CJM6C bảng dữ liệu(PDF) 100 Page - Freescale Semiconductor, Inc |
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PCIMX513CJM6C bảng dữ liệu(HTML) 100 Page - Freescale Semiconductor, Inc |
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100 / 184 page  i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 100 Freescale Semiconductor Preliminary—Subject to Change Without Notice Electrical Characteristics IP52 Write clock low pulse width Twl Tdicdw–Tdicuw–1.5 Tdicdw6–Tdicuw7 Tdicdw–Tdicuw+1.5 ns IP53 Write clock high pulse width Twh Tdicpw–Tdicdw+ Tdicuw–1.5 Tdicpw–Tdicdw+ Tdicuw Tdicpw–Tdicdw+ Tdicuw+1.5 ns IP54 Controls setup time for read Tdcsr Tdicur–1.5 Tdicur — ns IP55 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr — ns IP56 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw — ns IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns IP58 Slave device data delay8 Tracc 0 — Tdrp9–Tlbd10-Tdicur-1.5 ns IP59 Slave device data hold time8 Troh Tdrp-Tlbd-Tdicdr+1.5 — Tdicpr-Tdicdr-1.5 ns IP60 Write data setup time Tds Tdicdw-1.5 Tdicdw — ns IP61 Write data hold time Tdh Tdicpw-Tdicdw-1.5 Tdicpw-Tdicdw — ns IP62 Read period2 Tdicpr Tdicpr-1.5 Tdicpr Tdicpr+1.5 ns IP63 Write period3 Tdicpw Tdicpw-1.5 Tdicpw Tdicpw+1.5 ns IP64 Read down time4 Tdicdr Tdicdr-1.5 Tdicdr Tdicdr+1.5 ns IP65 Read up time5 Tdicur Tdicur-1.5 Tdicur Tdicur+1.5 ns IP66 Write down time6 Tdicdw Tdicdw-1.5 Tdicdw Tdicdw+1.5 ns IP67 Write up time7 Tdicuw Tdicuw-1.5 Tdicuw Tdicuw+1.5 ns IP68 Read time point9 Tdrp Tdrp-1.5 Tdrp Tdrp+1.5 ns IP69 Clock offset11 Toclk Toclk-1.5 Toclk Toclk+1.5 ns IP70 RS up time12 Tdicurs Tdicurs–1.5 Tdicurs Tdicurs+1.5 ns IP71 RS down time13 Tdicdrs Tdicdrs -1.5 Tdicdrs Tdicdrs+1.5 ns IP72 CS up time14 Tdicucs Tdicucs –1.5 Tdicucs Tdicucs+1.5 ns IP73 CS down time15 Tdicdcs Tdicdcs –1.5 Tdicdcs Tdicdcs+1.5 ns 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2Display interface clock period value for read 3Display interface clock period value for write Table 72. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued) ID Parameter Symbol Min Typ1 Max Unit Tdicpr T DI_CLK ceil × DISP#_IF_CLK_PER_RD DI_CLK_PERIOD -------------------------------------------------------------------- = Tdicpw T DI_CLK ce il × DISP#_IF_CLK_PER_WR DI_CLK_PERIOD ---------------------------------------------------------------------- = |
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