NJU6645 datasheet(21/112 Pages) NJRC

21 / 112 page

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Ver.2009-05-20

NJU6645

Preliminary

(2) ADDRESS COUNTER

The NJU6645 has the address counter of 12-bit for read/write of RAM data. The address is set by "RAM

address set" instruction. In case of the RDM=”0”, the address is incremented after the RAM data writing and

reading. In case of the RDM=”1”, the address is incremented only after the RAM data writing. The address

doesn't change after the RAM data reading.

The address shifts as follows within range of the address DDRAM, MKRAM, and CGRAM. The DDRAM

address shifts in each line.

DDRAM (1-line)

: (000)H

→ (001)H → --- → (01F)H → (000)H

DDRAM (2-line)

: (020)H

→ (021)H → --- → (03F)H → (020)H

DDRAM (3-line)

: (040)H

→ (041)H → --- → (05F)H → (040)H

DDRAM (4-line)

: (060)H

→ (061)H → --- → (07F)H → (060)H

DDRAM (5-line)

: (080)H

→ (081)H → --- → (09F)H → (080)H

DDRAM (6-line)

: (0A0)H

→ (0A1)H → --- → (0BF)H → (0A0)H

MKRAM

: (100)H

→ (101)H → --- → (13F)H → (100)H

CGRAM

: (200)H

→ (201)H → --- → (DFF)H → (200)H

The address is shifted to +1 or -1 by "address shift (ARL)" instruction. When ARL="0" is input, whenever it

is input the address is shifted -1. When ARL="1" is input, whenever it is input the address is shifted +1. The

address shifts as follows within range of the address DDRAM, MKRAM and CGRAM.

DDRAM (1-line)

: (000)H

↔ (001)H ↔ --- ↔ (01F)H ↔ (000)H

DDRAM (2-line)

: (020)H

↔ (021)H ↔ --- ↔ (03F)H ↔ (020)H

DDRAM (3-line)

: (040)H

↔ (041)H ↔ --- ↔ (05F)H ↔ (040)H

DDRAM (4-line)

: (060)H

↔ (061)H ↔ --- ↔ (07F)H ↔ (060)H

DDRAM (5-line)

: (080)H

↔ (081)H ↔ --- ↔ (09F)H ↔ (080)H

DDRAM (6-line)

: (0A0)H

↔ (0A1)H ↔ --- ↔ (0BF)H ↔ (0A0)H

MKRAM

: (100)H

↔ (101)H ↔ --- ↔ (13F)H ↔ (100)H

CGRAM

: (200)H

↔ (201)H ↔ --- ↔ (DFF)H ↔ (200)H

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