NJU6434

Ver.2009-11-12

-7 -

- Mode 5 : Shift Register 1~4 (D1~D200)

- Mode F : Shift Register 1~4 all “0”

Note 1) All of display data should be transmitted within 30ms to keep the display quality, because huge display

data D1 to D200 are transmitted at 4 times totally.

Note 2) Data is latched at the rising edge of the SCL.

Note 3) Mode data and display data are executed at the falling edge of the CE.

Note 4) In case of less than 4-bit data, the mode data remains the LSB side of the previous mode data.

Note 5) In case of over 4-bit data, the mode data is valid the previous 4-bit of the falling edge of the CE.

Note 6) In case of less than 50-bit data, the display data remains the last part of the previous display data.

Note 7) In case of over 50-bit data, the display data is valid the previous 50-bit of the falling edge of the CE.

(5) Initialization by Power On Reset

The NJU6434 incorporates the reset circuit of the detectable voltage type, and when the power supply is

turned on, it automatically initializes it (reset). When the VDD becomes 1V to 2.2V of the working voltage, the

reset signal is generated internally. When the power supplies rise time should be over than 0.1ms. (Refer to

“condition of the Power on reset” for details.)

(5-1) Status of Power On Reset

1. Mode setting release (nonselective status)

2. Shift register : all “0”

3. Latch circuit : all “0”

CE

SCL

DATA

MODE

D1

2

3

4

5

6

7

8

Mode Data

Display Data x 200-bit

194 195 196 19 7 1 9 8 199 200

1

0

1

0

CE

SCL

DATA

MODE

Mode Data

1

1

1

1

VDD=5V

VDD=3V

VDD=2.2V

Internal Reset wave

V

t