PCF8576DHSLASH2 datasheet(21/52 Pages) NXP

21 / 52 page

PCF8576D_9

Product data sheet

Rev. 09 — 25 August 2009

21 of 52

NXP Semiconductors

PCF8576D

Universal LCD driver for low multiplex rates

In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of

LCD segments can blink selectively by changing the display RAM data at ﬁxed time

intervals.

The entire display can blink at a frequency other than the nominal blink frequency by

sequentially resetting and setting the display enable bit E at the required rate using the

mode-set command (see Section 7.17).

[1]

Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator

frequency (fclk) of 1536 Hz (see Section 11).

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 13).

Table 6.

Blinking frequencies[1]

Blink mode

Normal operating mode ratio

Nominal blink frequency

off

blinking off

2 Hz

1 Hz

0.5 Hz

clk

768

----------

clk

1536

-------------

clk

3072

-------------

Fig 13. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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