PCA85133 datasheet(21/44 Pages) NXP

21 / 44 page

PCA85133_1

Product data sheet

Rev. 1 — 23 October 2009

21 of 44

NXP Semiconductors

PCA85133

Universal LCD driver for low multiplex rates

7.16.5 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.16.6 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA85133.

The least signiﬁcant bit of the slave address is bit R/W. The PCA85133 is a write-only

device. It will not respond to a read access, so this bit should always be logic 0. The

second bit of the slave address is deﬁned by the level tied at input SA0. Two types of

PCA85133 can be distinguished on the same I2C-bus which allows:

• Up to 16 PCA85133 on the same I2C-bus for very large LCD applications

• The use of two types of LCD multiplex drive modes on the same I2C-bus

The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the available PCA85133

slave addresses. All PCA85133 with the same SA0 level acknowledge in parallel to the

slave address. All PCA85133 with the alternative SA0 level ignore the whole I2C-bus

transfer.

After acknowledgement, the control byte is sent, deﬁning if the next byte is a RAM or

command information. The control byte also deﬁnes if the next byte is a control byte or

further RAM or command data (see Figure 16 and Table 8). In this way it is possible to

conﬁgure the device and then ﬁll the display RAM with little overhead.

Fig 15. I2C-bus protocol

EXAMPLES

a) transmit two bytes of RAM data

mgl752

S 0 1110

control byte

slave address

RAM/command byte

RAM DATA

R/W = 0

S 0 1110

0 1

RAM DATA

b) transmit two command bytes

COMMAND

S 0 1110

1 0

COMMAND

c) transmit one command byte and two RAM date bytes

COMMAND

S 0 1110

1 0

RAM DATA

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