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MCP4017 bảng dữ liệu(PDF) 10 Page - Microchip Technology |
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MCP4017 bảng dữ liệu(HTML) 10 Page - Microchip Technology |
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10 / 66 page  MCP4017/18/19 DS22147A-page 10 © 2009 Microchip Technology Inc. TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Parame- ter No. Sym Characteristic Min Max Units Conditions 100 THIGH Clock high time 100 kHz mode 4000 — ns 1.8V-5.5V 400 kHz mode 600 — ns 2.7V-5.5V 101 TLOW Clock low time 100 kHz mode 4700 — ns 1.8V-5.5V 400 kHz mode 1300 — ns 2.7V-5.5V 102A (5) TRSCL SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1Cb 300 ns 102B (5) TRSDA SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1Cb 300 ns 103A (5) TFSCL SCL fall time 100 kHz mode — 300 ns Cb is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1Cb 40 ns 103B (5) TFSDA SDA fall time 100 kHz mode — 300 ns Cb is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1Cb (4) 300 ns 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 1.8V-5.5V, Note 6 400 kHz mode 0 — ns 2.7V-5.5V, Note 6 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns (2) 400 kHz mode 100 — ns 109 TAA Output valid from clock 100 kHz mode — 3450 ns (1) 400 kHz mode — 900 ns 110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start 400 kHz mode 1300 — ns TSP Input filter spike suppression (SDA and SCL) 100 kHz mode — 50 ns Philips Spec states N.A. 400 kHz mode — 50 ns Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. 3: The MCP4018/MCP4019 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiv- ing device. 4: Use Cb in pF for the calculations. 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. |
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