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25LC040A bảng dữ liệu(PDF) 13 Page - Microchip Technology

tên linh kiện 25LC040A
Giải thích chi tiết về linh kiện  1K-4K SPI Serial EEPROM High Temp Family Data Sheet
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25LC040A bảng dữ liệu(HTML) 13 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
Preliminary
DS22136B-page 13
25LCXXXA
3.6
Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 3-3.
See Figure 3-6 for the WRSR timing sequence.
TABLE 3-3:
ARRAY PROTECTION
TABLE 3-4:
ARRAY PROTECTED ADDRESS LOCATIONS
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1
BP0
Array Addresses
Write-Protected
Array Addresses
Unprotected
00
None
All
01
Upper 1/4
Lower 3/4
10
Upper 1/2
Lower 1/2
11
All
None
Density
Upper 1/4
Upper 1/2
All
1K
60h - 7Fh
40h - 7Fh
00h - 7Fh
2K
C0h - FFh
80h - FFh
00h - FFh
4K
180h - 1FFh
100h - 1FFh
000h - 1FFh
SO
SI
CS
9
1011
12131415
0
1
0
0
0
0
00
76
5
4
21
0
Instruction
Data to STATUS Register
High-Impedance
SCK
0
2
34
56
7
1
8
3
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.



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