MCP6V01-ESLASHMD datasheet(6/44 Pages) MICROCHIP

6 / 44 page

MCP6V01/2/3

DS22058C-page 6

1.3

Timing Diagrams

FIGURE 1-1:

Amplifier Start Up.

FIGURE 1-2:

Offset Correction Settling

Time.

FIGURE 1-3:

Output Overdrive Recovery.

FIGURE 1-4:

Chip Select (MCP6V03).

1.4

Test Circuits

The circuits used for the DC and AC tests are shown in

Figure 1-5 and Figure 1-6. Lay the bypass capacitors

out as discussed in Section 4.3.8 “Supply Bypassing

and Filtering”. RN is equal to the parallel combination

of RF and RG to minimize bias current effects.

FIGURE 1-5:

AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

FIGURE 1-6:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

The circuit in Figure 1-7 tests the op amp input’s

dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The

potentiometer balances the resistor network (VOUT

should equal VREF at DC). The op amp’s common

mode input voltage is VCM =VIN/2. The error at the

input (VERR) appears at VOUT with a noise gain of

10 V/V.

FIGURE 1-7:

Test Circuit for Dynamic

Input Behavior.

VDD

VOS

VOS +50µV

VOS –50µV

tSTR

1.8V to 5.5V

1.8V

VIN

VOS

VOS +50µV

tSTL

VIN

VOUT

VDD

VSS

tODR

VDD/2

VIL

High-Z

tON

VIH

tOFF

VOUT

-2 µA

High-Z

ISS

-2 µA

300 µA

1µA

IDD

1µA

300 µA

VDD/5 MΩ

ICS

VDD/5 MΩ

5pA

(typical)

VDD

MCP6V0X

VOUT

VIN

VDD/3

1µF

100 nF

RISO

VDD

MCP6V0X

VOUT

VDD/3

VIN

1µF

100 nF

RISO

VDD

MCP6V0X

VOUT

1µF

100 nF

RISO

20.0 k

24.9

20.0 k

VIN

VREF

0.1%

25 turn

20.0 k

0.1%

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